1. Field of the Invention
The present invention relates to a semiconductor device that can be used effectively in a solid-state imaging device including: a photosensitive region in which a plurality of photosensitive cells are disposed in a matrix; a driving circuit for driving the plurality of photosensitive cells that is constituted by a dynamic circuit; a scanning circuit for selecting the plurality of photosensitive cells; and a bootstrap circuit for transmitting a selection signal from the scanning circuit to a driving circuit. In particular, the present invention relates to the bootstrap circuit.
2. Description of Related Art
In recent years, attention has been directed to a solid-state imaging apparatus provided with an amplification-type MOS sensor, as one of solid-state imaging apparatuses. In this solid-state imaging apparatus, a signal detected by a photodiode is amplified by a transistor for each cell (pixel), and the apparatus has a feature of high sensitivity. Such a solid-state imaging apparatus is provided with: an imaging portion having a multiplicity of pixels arranged two-dimensionally; and a dynamic-type shift register that scans horizontally or vertically, thus simplifying a circuit, increasing a density thereof and reducing power consumption.
Patent document 1 (JP 2004-312311 A) discloses an example of a solid-state imaging apparatus. The solid-state imaging apparatus disclosed in Patent document 1 includes: an imaging portion having a plurality of pixels; and a scanning circuit constituted by a dynamic logic circuit that outputs a selection signal for selecting a pixel in the imaging portion. This apparatus includes a bootstrap circuit between the scanning circuit and the imaging portion. The bootstrap circuit holds the selection signal from the scanning circuit in one horizontal scanning cycle, and then outputs, to the imaging portion, an AND result obtained by the thus held selection signal and a driving signal that designates an output signal to the imaging portion. The bootstrap circuit can select a desired pixel in the imaging portion, and can output an image signal based on the selected pixel.
FIG. 3 is a circuit diagram showing the configuration of a typical solid-state imaging apparatus. As shown in FIG. 3, several hundreds of thousands to several million photosensitive cells are disposed in matrix, each photosensitive cell including: a photodiode 11; a readout gate 12; an amplifier transistor 14; and a reset transistor 13. Thereby, a video signal with a high resolution can be obtained.
Each of the drains of the amplifier transistor 14 and the reset transistor 13 is connected to a common drain line 16. A source of the amplifier transistor 14 is connected to a vertical signal line 10. A load transistor 15 is connected to one end of the vertical signal line 10, and a noise removal circuit 18 is connected to the other end of the vertical signal line 10. An output line of the noise removal circuit 18 is connected to a horizontal transistor 20 that is driven by a horizontal driving circuit 19.
A vertical driving circuit 17 controls normal scanning and scanning for an electronic shutter with respect to a group of photosensitive cells, based on an output signal Reg-in from a scanning circuit (not shown in the figure) constituted by registers. Specifically, the vertical driving circuit 17 controls them so as to select a predetermined photosensitive cell at the time of scanning.
The horizontal driving circuit 19 controls the normal scanning and the scanning for the electronic shutter with respect to the group of photosensitive cells, based on the output signal Reg-in from the scanning circuit (not shown in the figure) constituted by the registers. Specifically, the horizontal driving circuit 19 controls them so as to select a predetermined row of photosensitive cells at the time of the scanning.
The bootstrap circuit is included in each of the horizontal driving circuit 19 and the vertical driving circuit 17, and is necessary for the horizontal transistor 20 and a read out pixel to achieve selecting actions efficiently. A configuration of the bootstrap circuit will be described below in detail.
The noise removal circuit 18 is disposed between the group of photosensitive cells and the horizontal transistor 20, and removes a noise component contained in a pixel signal that is output from the photosensitive cell.
The number of the disposed horizontal transistors 20 is equal to the number of the rows of the photosensitive cells, and each horizontal transistor 20 acts for selecting a predetermined row of pixels at the time of pixel selection. By switching on the horizontal transistor 20 that corresponds to the predetermined row of pixels based on a selection signal from the horizontal driving circuit 19, the predetermined row of pixels can be selected, and the pixel signal that is output from the photosensitive cell can be output from an output terminal 9.
FIG. 4 is a circuit diagram of the bootstrap circuit, and the bootstrap circuit includes: a selection transistor 21; a booster transistor 22; and a boosting capacitor 23. The boosting capacitor 23 is provided between a gate and a source of the booster transistor 22, and boosts a gate voltage by utilizing a voltage stored in the capacitor, thereby increasing a transmission efficiency between the drain and the source.
The actions will be described below.
For obtaining a pixel signal, by selecting the predetermined photosensitive cell from the group of photosensitive cells that are disposed in a matrix as shown in FIG. 3, the horizontal driving circuit 19 selects the predetermined row of photosensitive cells. Specifically, the selection transistor 21 in the bootstrap circuit that corresponds to the predetermined row of photosensitive cells, among the bootstrap circuits in the horizontal driving circuit 19, is switched on, based on the control signal Reg-in and a clock CLK from the scanning circuit (not shown in the figure).
Next, a voltage boosted by: an output control signal (hereinafter, called a Trans signal) to be input into the horizontal driving circuit 19; and the boosting capacitor 23 is input into the booster transistor 22. The booster transistor 22 outputs a difference between the input voltage and a threshold value (the selection signal for selecting the row of photosensitive cells). The horizontal selection transistor 20 acts based on the difference value that is output from the booster transistor 22, thereby selecting the predetermined row of photosensitive cells.
Moreover, the vertical driving circuit 17 selects the predetermined photosensitive cell from the row of photosensitive cells selected by the horizontal driving circuit 19. More specifically, the vertical driving circuit 17 outputs the selection signal from the bootstrap circuit that corresponds to the predetermined photosensitive cell to the photosensitive cell. Thereby, the predetermined photosensitive cell is selected. In addition, since an action of the bootstrap circuit in the vertical driving circuit 17 is the same as the above-described action of the bootstrap circuit in the horizontal driving circuit 19, explanations thereof will be omitted.
As mentioned above, the predetermined photosensitive cell (pixel) can be selected by the horizontal driving circuit 19 and the vertical driving circuit 17.
Next, the pixel signal that is photosensitized by the photodiode 11 in the selected photosensitive cell is amplified by the amplifier transistor 14, and is input into the noise removal circuit 18 via the vertical signal line 10. The noise removal circuit 18 removes a noise component of the input pixel signal, and outputs it from the output terminal 9 to the outside via the horizontal transistor 20.
Next, an action of the bootstrap circuit will be described in detail.
FIG. 5 is a timing chart showing the action of the bootstrap circuit. Firstly, when an input signal 31 (FIG. 5A) is input from a register (not shown in the figure) into a source of the selection transistor 21 at a timing t1, a gate of the selection transistor 21 is switched on based on a clock signal 32 (FIG. 5B), and the drain outputs an output signal 33 (FIG. 5C). The output signal 33 is input into a gate of the booster transistor 22, and since a voltage of the output signal 33 at this time is a threshold value of the booster transistor 22 or lower, the booster transistor 22 is in a state of off. Thereafter, the selection transistor 21 is in a state of off in one horizontal scanning cycle.
Next, at a timing t2, the Trans signal 34 (FIG. 5D) is input into the boosting capacitor 23 and the source of the booster transistor 22. When the Trans signal 34 is input, the voltage is boosted by the boosting capacitor 23, and the output signal 35 with the boosted voltage is input into the gate of the booster transistor 22. Thereby, the booster transistor 22 is switched on, and the drain outputs a selection signal 36 (FIG. 5E).
FIG. 6 is a cross-sectional view showing a configuration of transistor elements used in a conventional bootstrap circuit. In the figure, a selection transistor 49 corresponds to the selection transistor 21 of FIG. 4, and a booster transistor 50 corresponds to the booster transistor 22 of FIG. 4. A peripheral logic transistor 40 is mounted with the bootstrap circuit on the same substrate, but is used for circuits other than the bootstrap circuit.
In addition, the semiconductor device shown in this cross-sectional view is an MOS type solid-state imaging apparatus manufactured by utilizing a miniaturized CMOS logic technology with a size of 0.25 μm or less, in which STI (Shallow Trench Isolation) is used for element isolation and a gate oxide film is formed to have a thickness of 10 nm or less. A lamination structure includes: a p-well 42; an element isolation region 43 (hereinafter, called STI); a gate oxide film 44; a gate electrode 45; a side wall 46; a source/drain region 47; and an LDD (Lightly Doped Drain) region 48 that are formed in this order in a p-type silicone substrate 41. The selection transistor 49, the booster transistor 50 and the peripheral logic transistor 40 respectively are formed on the same substrate.
In FIG. 6, L4 and L7 respectively denote a gate length and a gate film thickness of the selection transistor 49, L5 denotes a gate length of the booster transistor 50, and L6 and L8 respectively denote a gate length and a gate film thickness of the peripheral logic transistor 40. Herein, a gate film thickness of the booster transistor 50 is equal to L7.
Since the selection transistor 49 and the booster transistor 50 constituting the bootstrap circuit are driven by the application of the high voltage boosted by the boosting capacitor 23 as mentioned above, L4 and L7 respectively are made to be larger than L6 and L8 of the peripheral logic transistor 40 so that the selection transistor 49 and the booster transistor 50 can resist the high voltage. As mentioned above, the bootstrap circuit is required to have a configuration that is capable of resisting the high voltage that is boosted in the circuit.
In addition, the transistor constituting the bootstrap circuit is required to ensure a drain withstand voltage, a sustain withstand voltage and the like against the input high voltage. The drain withstand voltage represents a drain voltage at the time when a predetermined amount of a current or more flows between the drain and the well, while increasing the drain voltage gradually in a state that each of a gate voltage, a source voltage and a well voltage is 0 V. The sustain withstand voltage represents a withstand voltage in the drain when the gate voltage is not 0 V, and accordingly, represents the gate voltage dependence of the drain withstand voltage.
In order to decrease the size of a solid-state imaging device more, the size of a transistor that is an element of the solid-state imaging device is required to be decreased more. However, there is a problem that the gate dimensions of the transistor used in the bootstrap circuit cannot be decreased so that the transistor may ensure its withstand voltage against the high voltage input thereto, and thus a size of the transistor cannot be decreased. That is, the configuration that can resist a high voltage in the transistor requires the large gate dimensions (the gate film thickness and the gate length).
In addition, although an increase of the number of pixels of the solid-state imaging device requires an increase of a speed of an action of the circuit, the gate dimensions (including the gate film thickness and the gate length) cannot be decreased in order to ensure the withstand voltage of the transistor, and thus there is a problem that it is difficult to increase the speed. That is, by increasing the gate dimensions (the gate film thickness and the gate length), a speed of response of the transistor decreases, which may prevent the increase of the speed of the solid-state imaging device.
Moreover, since the film thickness L7 and the film thickness L8 have different dimensions as shown in FIG. 6, in the case where the selection transistor 49, the booster transistor 50 and the peripheral logic transistor 40 are formed on the same substrate, additional processes such as mask alignment, washing, gate oxidation and resist removal are required for forming each of the gate oxide films having different film thicknesses, and thus there is a problem that the processes become complicated.